To meet customer demand for smaller and more power efficient integrated circuits (ICs), manufacturers are designing newer ICs that operate with lower supply voltages and that include smaller internal subcircuits such as memory cells. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more SRAM cells for data storage. SRAM cells are popular because they operate at a higher speed than dynamic-random-access-memory (DRAM) cells, and as long as they are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.
FIG. 1 is a circuit diagram of a conventional 6-transistor (6-T) SRAM cell 10, which can operate at a relatively low supply voltage, for example 2.2V-3.3V, but which is relatively large. A pair of NMOS access transistors 12 and 14 allow complementary bit values D and D on digit lines 16 and 18, respectively, to be read from and to be written to a storage circuit 20 of the cell 10. The storage circuit 20 includes NMOS pull-down transistors 22 and 26, which are coupled in a positive-feedback configuration with PMOS pull-up transistors 24 and 28. Nodes A and B are the complementary inputs/outputs of the storage circuit 20, and the respective complementary logic values at these nodes represent the state of the cell 10. For example, when the node A is at logic 1 and the node B is at logic 0, then the cell 10 is storing a logic 1. Conversely, when the node A is at logic 0 and the node B is at logic 1, then the cell 10 is storing a logic 0. Thus, the cell 10 is bistable, i.e., can have one of two stable states, logic 1 or logic 0.
In operation during a read of the cell 10, a word-line WL, which is coupled to the gates of the transistors 12 and 14, is driven to a voltage approximately equal to Vcc to activate the transistors 12 and 14. For example purposes, assume that Vcc=logic 1=5V and Vss=logic 0=0V, and that at the beginning of the read, the cell 10 is storing a logic 0 such that the voltage level at the node A is 0V and the voltage level at the node B is 5V. Also, assume that before the read cycle, the digit lines 16 and 18 are equilibrated to approximately Vcc. Therefore, the NMOS transistor 12 couples the node A to the digit line 16, and the NMOS transistor 14 couples the node B to the digit line 18. For example, assuming that the threshold voltages of the transistors 12 and 14 are both 1V, then the transistor 14 couples a maximum of 4V from the digit line 18 to the node B. The transistor 12, however, couples the digit line 16 to the node A, which pulls down the voltage on the digit line 16 enough (for example, 100-500 millivolts) to cause a sense amp (not shown) coupled to the lines 16 and 18 to read the cell 10 as storing a logic 0.
In operation during a write, for example, of a logic 1 to the cell 10, and making the same assumptions as discussed above for the read, the transistors 12 and 14 are activated as discussed above, and logic 1 is driven onto the digit line 16 and a logic 0 is driven onto the digit line 18. Thus, the transistor 12 couples 4V (the 5V on the digit line 16 minus the 1V threshold of the transistor 12) to the node A, and the transistor 14 couples 0V from the digit line 18 to the node B. The low voltage on the node B turns off the NMOS transistor 26, and turns on the PMOS transistor 28. Thus, the inactive NMOS transistor 26 allows the PMOS transistor 28 to pull the node A up to 5V. This high voltage on the node A turns on the NMOS transistor 22 and turns off the PMOS transistor 24, thus allowing the NMOS transistor 22 to reinforce the logic 0 on the node B. Likewise, if the voltage written to the node B is 4V and that written to the node A is 0V, the positive-feedback configuration ensures that the cell 10 will store a logic 0.
Because the PMOS transistors 26 and 28 have low on resistances (typically on the order of a few kilohms), they can pull the respective nodes A and B virtually all the way up to Vcc often in less than 10 nanoseconds (ns), and thus render the cell 10 relatively stable and allow the cell 10 to operate at a low supply voltage as discussed above. But unfortunately, the transistors 26 and 28 cause the cell 10 to be approximately 30%-40% larger than a 4-transistor (4-T) SRAM cell, which is discussed next.
FIG. 2 is a circuit diagram of a conventional 4-T SRAM cell 30, where elements common to FIGS. 1 and 2 are referenced with like numerals. A major difference between the 6-T cell 10 and the 4-T cell 30 is that the PMOS pull-up transistors 26 and 28 of the 6-T cell 10 are replaced with conventional passive loads 32 and 34. For example, the loads 32 and 34 are often polysilicon resistors. Otherwise the topologies of the 6-T cell 10 and the 4-T cell 30 are the same. Furthermore, the 4-T cell 30 operates similarly to the 6-T cell 10. Because the loads 32 and 34 are usually built in another level above the access transistors 12 and 14 and the NMOS pull-down transistors 22 and 26, the 4-T cell 30 usually occupies much less area than the 6-T cell 10. But as discussed below, the high resistance values of the loads 32 and 34 can substantially lower the stability margin of the cell 30 as compared with the cell 10. Thus, under certain conditions, the cell 30 can inadvertently become monostable or read unstable instead of bistable. Also, the cell 30 consumes more power than the cell 20 because there is always current flowing from Vcc to Vss through either the load 32 and the NMOS transistor 24 or the load 34 and the NMOS transistor 22. In contrast, current flow from Vcc to Vss in the cell 20 is always blocked by one of the NMOS/PMOS transistor pairs 22/24 and 26/28.
Still referring to FIG. 2, the cell 30 is monostable when it can store only one logic state instead of two when the access transistors 12 and 14 are in the off state. More specifically, in order to minimize the quiescent current, and thus the quiescent power, drawn by the cell 30, the loads 32 and 34 have relatively high resistance values, often on the order of megaohms or gigaohms. But offset currents, typically on the order of picoamps (pA), often flow from the nodes A and B. These offset currents are typically due to the leakage currents, the subthreshold currents, or both generated by the transistors 12, 14, 22, and 24 when they are in an off state. To prevent these offset currents from causing the cell 30 to spontaneously change states, the loads 32 and 34 must have values low enough so that when the transistors 12 and 26 and 14 and 22 are off, the currents that flow from Vcc to the nodes A and B are greater than or equal to these respective offset currents. For example, suppose that initially the cell 30 is storing a logic 1 such that the voltage at the node A is approximately 5V and the voltage at the node B is approximately 0V. Furthermore, suppose that the total offset current drawn from the node A is 10 pA. If the load 32 allows only 5 pA to flow from Vcc to the node A, then the larger offset current will gradually discharge the parasitic capacitance (not shown in FIG. 2) associated with the node A, thus lowering the voltage at the node A until the transistor 22 turns off. At this point, assuming that the current through the load 34 is greater than the offset current drawn from the node B, then the voltage at the node B gradually increases until the transistor 26 turns on and thus pulls the node A to 0V. Thus, in this example, the cell 30 has only one stable state, logic 0, when the access transistors 12 and 14 are off, and is therefore monostable. That is, even if a logic 1 is written to it, the cell 30 will eventually and spontaneously flip to a logic 0.
Still referring to FIG. 2, even when the cell 30 is bistable, it may still be read unstable. Read instability occurs when the cell 30 has only one stable logic state when the access transistors 12 and 14 are on, as they are during a read. Therefore, the cell 30 may be able to stably store a logic 1 or logic 0 that is written to it, but when the access transistors 12 and 14 are activated during a read (when there are no write voltages driven onto the digit lines 16 and 18), the cell 30 becomes read-monostable. If the logic state last written to the cell 30 is opposite the read-monostable state, then the cell 30 will spontaneously flip states.
FIG. 3A is a graph showing the behavior of a first branch of the cell 30 that includes the access transistor 12 and the pull-down transistor 26. V.sub.A is the voltage at the node A of FIG. 2, and V.sub.B is the voltage at the node B, which is also the input voltage to the gate of the transistor 26. Region C is where the transistor 12 is on and the transistor 26 is off, region B is where both the transistors 12 and 26 are on and in saturation, and region E is where both the transistors 12 and 26 are on but the transistor 26 is in the linear region, thus forcing node A to a low value. Processing variations in the transistors 12 and 26, or changes in Vcc, the back-bias voltage applied to the substrate (not shown in FIG. 2) of the circuit, or in the voltage at the node A immediately after the transistor 12 is turned on may change the shape of the curve. Furthermore, a similar analysis of a second branch of the cell 30 that includes the access transistor 14 and the pull-down transistor 22 yields a similar curve.
FIG. 3B shows the curve for the first branch of the cell 30 overlaid with the curve for the second branch of the cell 30 when the cell 30 is read stable. Point F is the stable logic 1 state of the cell 30 where the voltage at the node A (V.sub.A1) is logic 1, and the voltage at the node B (V.sub.B1) is logic 0. Point G represents the metastable midpoint where both nodes A and B are equal. Point H is the stable logic 0 state of the cell 30 where the voltage at the node A (V.sub.A0) is logic 0 and the voltage at the node B (V.sub.B0) is logic 1. The distances I and J are the maximum widths of the respective lobes formed by the overlaid curves. The smaller of the distances I and J is sometimes referred to as the static noise margin (SNM), which is a measure of the stability of the cell 30.
FIG. 3C is an overlay of the curves of FIG. 3B when the cell 30 is read unstable and has only one stable point F when the transistors 12 and 14 are on. A reduction in Vcc will reduce the heights of the curves of FIGS. 3A and 3B, and thus increase the chances of read instability. Furthermore, because the transistors 12 and 14 are NMOS transistors, the maximum logic 1 voltage that can be coupled to the nodes A and B (from the equilibrated digit lines 16 and 18, respectively) during a read is Vcc minus the threshold of the respective transistor 12 and 14. This also reduces the heights of the curves of FIGS. 3A and 3B, and thus also increases the chances of read instability. Furthermore, as discussed in more detail below, a low logic 1 voltage at the node A or B immediately following the activation of the access transistors 12 or 14, respectively, may cause such a reduction in the height of the curves. For example, again referring to FIG. 2, assume that the offset current drawn from the node A is 10 pA, but that the load 32 allows a current greater than 10 pA, e.g., 12-15 pA, to flow from Vcc to the node A such that the cell 30 is bistable when the transistors 12 and 14 are off. Furthermore, assume that a logic 1 is written to the cell 30, and that as above, Vcc=logic 1=5V, Vss=logic 0=0V, and the thresholds of the transistors 12 and 14=1V. During such a write, approximately 4V (5V on the digit line 16 minus the 1V threshold of the transistor 12) is coupled to the node A and approximately 0V is coupled to the node B from the digit line via the transistor 14. Next, assume that before the positive feedback action of the circuit 21 has a chance to fully charge the node A to 5V (this could take on the order of one nanosecond), the cell 30 is read. (A read may occur tens to hundreds of nanoseconds after a write.) Thus, the effective lowering of the voltage on the node A from 5 volts to 4 volts after the transistors 12 and 14 are activated may be sufficient to cause the cell 30 to have the characteristics shown in FIG. 3C, thus causing the cell 30 to be read unstable.
Therefore, as stated above, as Vcc is reduced, the probability increases that the cell 30 may be either monostable or read unstable. Thus, although the 4-T cell 30 is physically smaller than the 6-T cell 10 of FIG. 1, it is much less suitable for operation at low supply voltages.